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1. general description the PCA9600 is designed to isolate i 2 c-bus capacitance, allowing long buses to be driven in point-to-point or multipoint applications of up to 4000 pf. the PCA9600 is a higher-speed version of the p82b96. it creates a non-latching, bidirectional, logic interface between a normal i 2 c-bus and a range of other higher capacitance or different voltage bus con?gurations. it can operate at speeds up to at least 1 mhz, and the high drive side is compatible with the fast-mode plus (fm+) speci?cations. the PCA9600 features temperature-stabilized logic voltage levels at its sx/sy interface making it suitable for interfacing with buses that have non i 2 c-bus-compliant logic levels such as smbus, pmbus, or with microprocessors that use those same ttl logic levels. the separation of the bidirectional i 2 c-bus signals into unidirectional tx and rx signals enables the sda and scl signals to be transmitted via balanced transmission lines (twisted pairs), or with galvanic isolation using opto or magnetic coupling. the tx and rx signals may be connected together to provide a normal bidirectional signal. 2. features n bidirectional data transfer of i 2 c-bus signals n isolates capacitance allowing 400 pf on sx/sy side and 4000 pf on tx/ty side n tx/ty outputs have 60 ma sink capability for driving low-impedance or high-capacitive buses n 1 mhz operation on up to 20 meters of wire (see an10658 ) n supply voltage range of 2.5 v to 15 v with i 2 c-bus logic levels on sx/sy side independent of supply voltage n splits i 2 c-bus signal into pairs of forward/reverse tx/rx, ty/ry signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths n low power supply current n esd protection exceeds 4500 v hbm per jesd22-a114, 450 v mm per jesd22-a115, and 1400 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n packages offered: so8 and tssop8 (msop8) PCA9600 dual bidirectional bus buffer rev. 04 11 november 2009 product data sheet
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 2 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 3. applications n interface between i 2 c-buses operating at different logic levels (for example, 5 v and 3 v or 15 v) n interface between i 2 c-bus and smbus (350 m a) standard or fm+ standard n simple conversion of i 2 c-bus sda or scl signals to multi-drop differential bus hardware, for example, via compatible pca82c250 n interfaces with opto-couplers to provide opto-isolation between i 2 c-bus nodes up to 1 mhz n long distance point-to-point or multipoint architectures 4. ordering information 4.1 ordering options 5. block diagram table 1. ordering information type number package name description version PCA9600d so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1 PCA9600dp tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 table 2. ordering options type number topside mark temperature range PCA9600d PCA9600 - 40 c to +85 c PCA9600dp 9600 - 40 c to +85 c fig 1. block diagram of PCA9600 PCA9600 sx (sda) rx (rxd, sda) sy (scl) tx (txd, sda) ty (txd, scl) gnd ry (rxd, scl) 002aac835 v cc (2.5 v to 15 v) 8 1 7 4 3 2 5 6
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 3 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 6. pinning information 6.1 pinning 6.2 pin description 7. functional description refer to figure 1 bloc k diag r am of PCA9600 . the PCA9600 has two identical buffers allowing buffering of sda and scl i 2 c-bus signals. each buffer is made up of two logic signal paths, a forward path from the i 2 c-bus interface, pins sx and sy which drive the buffered bus, and a reverse signal path from the buffered bus input, pins rx and ry to drive the i 2 c-bus interface. these paths: ? sense the voltage state of i 2 c-bus pins sx (and sy) and transmit this state to pin tx (and ty respectively), and ? sense the state of pins rx and ry and pull the i 2 c-bus pin low whenever pin rx or pin ry is low. the rest of this discussion will address only the x side of the buffer; the y side is identical. the i 2 c-bus pin sx is speci?ed to allow interfacing with fast-mode, fm+ and ttl-based systems. fig 2. pin con?guration for so8 fig 3. pin con?guration for tssop8 (msop8) PCA9600d sx v cc rx sy tx ry gnd ty 002aac836 1 2 3 4 6 5 8 7 PCA9600dp sx v cc rx sy tx ry gnd ty 002aac837 1 2 3 4 6 5 8 7 table 3. pin description symbol pin description sx 1 i 2 c-bus (sda or scl) rx 2 receive signal tx 3 transmit signal gnd 4 negative supply voltage ty 5 transmit signal ry 6 receive signal sy 7 i 2 c-bus (sda or scl) v cc 8 positive supply voltage
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 4 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer the logic threshold voltage levels at sx on this i 2 c-bus are independent of the ic supply voltage v cc . the maximum i 2 c-bus supply voltage is 15 v. when interfacing with fast-mode systems, the sx pin is guaranteed to sink the normal 3 ma with a v ol of 0.74 v maximum. that guarantees compliance with the fast-mode i 2 c-bus speci?cation for all i 2 c-bus voltages greater than 3 v, as well as compliance with smbus or other systems that use ttl switching levels. sx is guaranteed to sink an external 3 ma in addition to its internally sourced pull-up of typically 300 m a (maximum 1 ma at - 40 c). when selecting the pull-up for the bus at sx, the sink capability of other connected drivers should be taken into account. most ttl devices are speci?ed to sink at least 4 ma so then the pull-up is limited to 3 ma by the requirement to ensure the 0.8 v ttl low. for fast-mode i 2 c-bus operation, the other connected i 2 c-bus parts may have the minimum sink capability of 3 ma. sx sources typically 300 m a (maximum 1 ma at - 40 c), which forms part of the external driver loading. when selecting the pull-up it is necessary to subtract the sx pin pull-up current, so, worst-case at - 40 c, the allowed pull-up can be limited (by external drivers) to 2 ma. when the interface at sx is an fm+ bus with a voltage greater than 4 v, its higher speci?ed sink capability may be used. PCA9600 has a guaranteed sink capability of 7 ma at v ol = 1 v maximum. that 1 v complies with the bus low requirement (0.25v bus ) of any fm+ bus operating at 4 v or greater. since the other connected fm+ devices have a drive capability greater than 20 ma, the pull-up may be selected for 7 ma sink current at v ol = 1 v. for a nominal 5 v bus (5.5 v maximum) the allowed pull-up is (5.5 v - 1v)/7ma=643 w . with 680 w pull-up, the fm+ rise time of 120 ns maximum can be met with total bus loading up to 200 pf. the logic level on rx is determined from the power supply voltage v cc of the chip. logic low is below 40 % of v cc , and logic high is above 55 % of v cc (with a typical switching threshold just slightly below half v cc ). tx is an open-collector output without esd protection diodes to v cc . it may be connected via a pull-up resistor to a supply voltage in excess of v cc , as long as the 15 v rating is not exceeded. it has a larger current sinking capability than a normal i 2 c-bus device, being able to sink a static current of greater than 30 ma, and typical 100 ma dynamic pull-down capability as well. a logic low is transmitted to tx when the voltage at i 2 c-bus pin sx is below 0.425 v. a logic low at rx will cause i 2 c-bus pin sx to be pulled to a logic low level in accordance with i 2 c-bus requirements (maximum 1.5 v in 5 v applications) but not low enough to be looped back to the tx output and cause the buffer to latch low. the low level this chip can achieve on the i 2 c-bus by a low at rx is typically 0.64 v when sinking 1 ma. if the supply voltage v cc fails, then neither the i 2 c-bus nor the tx output will be held low. their open-collector con?guration allows them to be pulled up to the rated maximum of 15 v even without v cc present. the input con?guration on sx and rx also presents no loading of external signals when v cc is not present. the effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 10 pf for all bus voltages and supply voltages including v cc =0v.
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 5 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer remark: two or more sx or sy i/os must not be interconnected. the PCA9600 design does not support this con?guration. bidirectional i 2 c-bus signals do not allow any direction control pin so, instead, slightly different logic low voltage levels are used at sx/sy to avoid latching of this buffer. a regular i 2 c-bus low applied at the rx/ry of a PCA9600 will be propagated to sx/sy as a buffered low with a slightly higher voltage level. if this special buffered low is applied to the sx/sy of another PCA9600, that second PCA9600 will not recognize it as a regular i 2 c-bus low and will not propagate it to its tx/ty output. the sx/sy side of PCA9600 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example p82b96, pca9511a, pca9515a, b side of pca9517, etc. the sx/sy side is only intended for, and compatible with, the normal i 2 c-bus logic voltage levels of i 2 c-bus master and slave chips, or even tx/rx signals of a second PCA9600 or p82b96 if required. the tx/rx and ty/ry i/o pins use the standard i 2 c-bus logic voltage levels of all i 2 c-bus parts. there are no restrictions on the interconnection of the tx/rx and ty/ry i/o pins to other PCA9600s, for example in a star or multipoint con?guration with the tx/rx and ty/ry i/o pins on the common bus and the sx/sy side connected to the line card slave devices. for more details see application note an10658, sending i 2 c-bus signals via long communication cables . the PCA9600 is a direct upgrade of the p82b96 with the signi?cant differences summarized in t ab le 4 . table 4. PCA9600 versus p82b96 detail PCA9600 p82b96 supply voltage (v cc ) range: 2.5 v to 15 v 2 v to 15 v maximum operating bus voltage (independent of v cc ): 15 v 15 v typical operating supply current: 5 ma 1 ma typical low-level input voltage on i 2 c-bus (sx/sy side): 0.5 v over - 40 c to +85 c 0.65 v at 25 c low-level output voltage on i 2 c-bus (sx/sy side; 3 ma sink): 0.74 v (max.) over - 40 c to +85 c 0.88 v (typ.) at 25 c low-level output voltage on fm+ i 2 c-bus (sx/sy side; 7 ma sink): 1 v (max.) n/a temperature coef?cient of v il /v ol : 0 mv/ c - 2 mv/ c logic voltage levels on sx/sy bus (independent of v cc ): compatible with i 2 c-bus and similar buses using ttl levels (smbus, etc.) compatible with i 2 c-bus and similar buses using ttl levels (smbus, etc.) typical propagation delays: < 100 ns < 200 ns tx/rx switching speci?cations (i 2 c-bus compliant): yes, all classes including 1 mhz fm+ yes, all classes including fm+ rx logic levels with tighter control than i 2 c-bus limit of 30 % to 70 %: yes, 40 % to 55 % (48 % nominal) yes, 42 % to 58 % (50 % nominal) maximum bus speed: > 1 mhz > 400 khz esd rating hbm per jesd22-a114: > 4500 v > 3500 v package: so8, tssop8 (msop8) dip8, so8, tssop8 (msop8)
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 6 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer when the device driving the PCA9600 is an i 2 c-bus compatible device, then the PCA9600 is an improvement on the p82b96 as shown in t ab le 4 . there will always be exceptions however, and if the device driving the bus buffer is not i 2 c-bus compatible (e.g., you need to use the micro already in the system and bit-bang using two gpio pins) then here are some considerations that would point to using the p82b96 instead: ? when the pull-up must be the weakest one possible. the spec is 200 m a for p82b96, but it typically works even below that. and if designing for a temperature range - 40 c up to +60 c, then the driver when sinking 200 m a only needs to drive a guaranteed low of 0.55 v. for the PCA9600, over that same temperature range and when sinking 1.3 ma (at - 40 c), the device driving the bus buffer must provide the required low of 0.425 v. ? when the lower operating temperature range is restricted (say 0 c). the p82b96 larger sx voltage levels then make a better typical match with the driver, even when the supply is as low as 3.3 v. for an i 2 c-bus compliant driver on 3.3 v the p82b96 is required to guarantee a bus low that is below 0.83 v. p82b96 guarantees that with a 200 m a pull-up. ? when the operating temperature range is restricted at both limits. an i 2 c driver's typical output is well below 0.4 v and the p82b96 typically requires 0.6 v input even at +60 c, so there is a reasonable margin. the PCA9600 requires a typical input low of 0.5 v so its typical margin is smaller. at 0 c the driver requires a typical input low of 1.16 v and p82b96 provides 0.75 v, so again the typical margin is already quite big and even though PCA9600 is better, providing 0.7 v, that difference is not big. 8. limiting values [1] see also section 10.2 negativ e undershoot belo w absolute minim um v alue . table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages with respect to pin gnd. symbol parameter conditions min max unit v cc supply voltage v cc to gnd - 0.3 +18 v v i2c-bus i 2 c-bus voltage sx and sy; i 2 c-bus sda or scl - 0.3 +18 v v o output voltage tx and ty; buffered output [1] - 0.3 +18 v v i input voltage rx and ry; receive input [1] - 0.3 +18 v i i2c-bus i 2 c-bus current sx and sy; i 2 c-bus sda or scl - 250 ma p tot total power dissipation - 300 mw t j junction temperature operating range - 40 +125 c t stg storage temperature - 55 +125 c t amb ambient temperature operating - 40 +85 c
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 7 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 9. characteristics table 6. characteristics t amb = - 40 c to +85 c unless otherwise speci?ed; voltages are speci?ed with respect to gnd with v cc = 2.5 v to 15 v unless otherwise speci?ed. typical values are measured at v cc = 5 v and t amb =25 c. symbol parameter conditions min typ max unit power supply v cc supply voltage operating 2.5 - 15 v i cc supply current v cc = 5 v; buses high - 5.2 6.75 ma v cc = 15 v; buses high - 5.5 7.3 ma d i cc additional supply current per tx/ty output driven low; v cc = 5.5 v - 1.4 3.0 ma bus pull-up (load) voltages and currents pins sx and sy; i 2 c-bus v i input voltage open-collector; rx and ry high --15v v o output voltage open-collector; rx and ry high --15v i o output current static; v sx = v sy = 0.4 v [1] 0.3 - 2 ma i o(sink) output sink current dynamic; v sx = v sy = 1 v; rx and ry low 715- ma i l leakage current v sx = v sy = 15 v; rx and ry high --10 m a pins tx and ty v o output voltage open-collector - - 15 v i load load current maximum recommended on buffered bus; v tx =v ty = 0.4 v; sx and sy low on i 2 c-bus = 0.4 v --30ma i o output current from buffered bus; dynamic; v tx = v ty = 1 v; sx and sy low on i 2 c-bus = 0.4 v 60 130 - ma i l leakage current on buffered bus; v tx =v ty =v cc =15v; sx and sy high --10 m a input currents i i input current from i 2 c-bus on sx and sy rx and ry high or low; sx and sy low 1v [1] - - 0.3 - 1ma rx and ry high; sx and sy high > 1.4 v [1] --10 m a from buffered bus on rx and ry; sx and sy high or low; v rx =v ry = 0.4 v [2] - - 1.5 - 10 m a i l leakage current on buffered bus input on rx and ry; v rx = v ry =15v --10 m a
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 8 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer output logic low level pins sx and sy v ol low-level output voltage on standard-mode or fast-mode i 2 c-bus i sx =i sy = 3 ma; figure 6 - 0.7 0.74 v i sx =i sy = 0.3 ma; figure 5 - 0.6 0.65 mv on 5 v fm+ i 2 c-bus i sx =i sy = 7 ma - - 1 v d v/ d t voltage variation with temperature i sx =i sy = 0.3 ma to 3 ma - 0 - %/k input logic switching threshold voltages pins sx and sy v il low-level input voltage on normal i 2 c-bus; figure 7 [3] 425 500 - mv v th(ih) high-level input threshold voltage on normal i 2 c-bus; figure 8 - 500 580 mv d v/ d t voltage variation with temperature - 0 - %/k pins rx and ry v ih high-level input voltage fraction of applied v cc 0.55v cc --v v th(i) input threshold voltage fraction of applied v cc - 0.48v cc -v v il low-level input voltage fraction of applied v cc - - 0.4v cc v logic level threshold difference d v voltage difference sx and sy; sx output low at 0.3 ma to sx input high maximum [4] 50--mv thermal resistance r th(j-pcb) thermal resistance from junction to printed-circuit board sot96-1 (so8); average lead temperature at board interface - 127 - k/w bus release on v cc failure v cc supply voltage sx, sy, tx and ty; voltage at which all buses are to be released at 25 c --1v d v/ d t voltage variation with temperature figure 9 - - 4 - %/k table 6. characteristics continued t amb = - 40 c to +85 c unless otherwise speci?ed; voltages are speci?ed with respect to gnd with v cc = 2.5 v to 15 v unless otherwise speci?ed. typical values are measured at v cc = 5 v and t amb =25 c. symbol parameter conditions min typ max unit
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 9 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer [1] the maximum static sink current for a standard i 2 c-bus is 3 ma and PCA9600 is guaranteed to sink 3 ma at sx/sy when those pins are holding the bus low. however, when an external device pulls the sx/sy pins below 1.4 v, the PCA9600 may source a current between 0 ma and 1 ma maximum. during contention an external device is required to pull the bus connected to sx or sy down to the 0.4 v level referenced in the i 2 c-bus speci?cation. so that device must be able to sink up to 1 ma from sx/sy plus the usual pull-up current. therefore the external pull-up used at sx/sy should be limited to 2 ma. the typical and maximum currents sourced by sx/sy as a function of junction temperature are shown in figure 10 , and the equivalent circuit at the sx/sy interface is shown in figure 4 . [2] valid over temperature for v cc 5 v. at higher v cc , this current may increase to maximum - 20 m a at v cc =15v. [3] the input logic threshold is independent of the supply voltage. [4] the minimum value requirement for pull-up current, 0.3 ma, guarantees that the minimum value for v sx output low will always exceed the maximum v sx input high level to eliminate any possibility of latching. the speci?ed difference is guaranteed by design within any ic. while the tolerances on absolute levels allow a small probability, the low from one sx output is recognized by an sx input of another PCA9600, this has no consequences for normal applications. in any design the sx pins of different ics should never be l inked because the resulting system would be very susceptible to induced noise and would not support all i 2 c-bus operating modes. [5] the fall time of v tx from 5 v to 2.5 v in the test is approximately 10 ns. the fall time of v sx from 5 v to 2.5 v in the test is approximately 20 ns. the rise time of v tx from 0 v to 2.5 v in the test is approximately 15 ns. the rise time of v sx from 0.7 v to 2.5 v in the test is approximately 25 ns. buffer response time [5] v cc = 5 v; pin tx pull-up resistor = 160 w ; pin sx pull-up resistor = 2.2 k w ; no capacitive load t d delay time v sx to v tx , v sy to v ty ; on falling input between v sx = input switching threshold, and v tx output falling to 50 % v cc -50-ns v sx to v tx , v sy to v ty ; on rising input between v sx = input switching threshold, and v tx output reaching 50 % v cc -60-ns v rx to v sx , v ry to v sy ; on falling input between v rx = input switching threshold, and v sx output falling to 50 % v cc - 100 - ns v rx to v sx , v ry to v sy ; on rising input between v rx = input switching threshold, and v sx output reaching 50 % v cc -95-ns input capacitance c i input capacitance effective input capacitance of any signal pin measured by incremental bus rise times; guaranteed by design, not production tested --10pf table 6. characteristics continued t amb = - 40 c to +85 c unless otherwise speci?ed; voltages are speci?ed with respect to gnd with v cc = 2.5 v to 15 v unless otherwise speci?ed. typical values are measured at v cc = 5 v and t amb =25 c. symbol parameter conditions min typ max unit
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 10 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer fig 4. equivalent circuit at sx/sy 002aac838 v cc 1 ma sx (sy) v ref v ol at sx typical and limits over temperature. (1) maximum. (2) typical. v ol at sx typical and limits over temperature. (1) maximum. (2) typical. fig 5. v ol as a function of junction temperature (i ol = 0.3 ma) fig 6. v ol as a function of junction temperature (i ol = 3 ma) v il at sx changes over temperature range. v ih at sx changes over temperature range. fig 7. v il as a function of junction temperature; maximum values fig 8. v ih as a function of junction temperature; minimum values 800 v ol (mv) 400 t j ( c) 002aac839 (1) - 50 125 100 75 50 25 0 - 25 (2) 600 500 700 800 v ol (mv) 400 t j ( c) 002aac840 (1) - 50 125 100 75 50 25 0 - 25 (2) 600 500 700 600 v il (mv) 200 t j ( c) 001aai060 500 400 300 - 50 125 100 75 50 25 0 - 25 600 v ih (mv) 200 t j ( c) 001aai061 500 400 300 - 50 125 100 75 50 25 0 - 25
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 11 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer (1) maximum. (2) typical. fig 9. v cc bus release limit over temperature; maximum values fig 10. current sourced out of sx/sy as a function of junction temperature if these pins are externally pulled to 0.4 v or lower 600 1400 v cc(max) (mv) 400 t j ( c) 002aac075 - 50 125 100 75 50 25 0 - 25 800 1000 1200 200 1000 i i ( m a) 0 t j ( c) 001aai062 - 50 125 100 75 50 25 0 - 25 400 600 800 (1) (2)
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 12 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 10. application information refer to PCA9600 data sheet and application notes an10658 and an255 for more detailed application information. fig 11. interfacing a standard 3 ma i 2 c-bus or one with ttl levels (e.g. smbus) to higher voltage or higher current sink (e.g. fast-mode plus) devices this simple example may be limited, if using lowest-cost couplers, to speeds as low as 5 khz. refer to application notes for schematics suitable for operation to 400 khz or higher. fig 12. galvanic isolation of i 2 c-bus nodes via opto-couplers fig 13. long distance i 2 c-bus communication PCA9600 i 2 c-bus sda 001aai063 5 v v cc (2.5 v to 15 v) r1 rx (sda) tx (sda) 'sda' (new levels) PCA9600 i 2 c-bus sda 001aai064 5 v r1 v cc r2 r3 rx (sda) tx (sda) r5 r4 v cc1 i 2 c-bus sda PCA9600 sda scl 002aac846 12 v 12 v 3.3 v to 5 v 3.3 v to 5 v long cables main enclosure PCA9600 sda scl 3.3 v to 5 v 3.3 v to 5 v remote control enclosure 12 v
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 13 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer for more examples of faster alternatives for driving over longer cables such as cat5 communication cable, see an10658 . communication at 1 mhz is possible over short cables and > 400 khz is possible over 50 m of cable. fig 14. driving ribbon or ?at telephone cables PCA9600 scl rx tx 002aac851 sx v cc ty ry sy r2 r2 c2 c2 i 2 c-bus master sda v cc1 gnd r1 r1 bat54a cable propagation delay ? 5 ns/m bat54a r1 r1 PCA9600 rx tx ty ry v cc sx sy r2 r2 scl sda v cc2 gnd i 2 c-bus slave(s) c2 c2 +v cable drive table 7. examples of bus capability refer to figure 14 . v cc1 (v) +v cable (v) v cc2 (v) r1 ( w ) r2 (k w ) c2 (pf) cable length (m) cable capacitance cable delay set master nominal scl effective bus clock speed (khz) max. slave response delay high period (ns) low period (ns) 5 12 5 750 2.2 400 250 n/a (delay based) 1.25 m s 600 3850 125 normal speci?cation 400 khz parts 5 12 5 750 2.2 220 100 n/a (delay based) 500 ns 600 2450 195 normal speci?cation 400 khz parts 3.3 5 3.3 330 1 220 25 1 nf 125 ns 260 770 620 meets fm+ speci?cation 3.3 5 3.3 330 1 100 3 120 pf 15 ns 260 720 690 meets fm+ speci?cation
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 14 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 10.1 calculating system delays and bus clock frequency effective delay of scl at slave: 120 + 17v ccm + (2.5 + 4 10 9 c b ) v ccb + 10v ccs (ns). c = f; v = v. fig 15. falling edge of scl at master is delayed by the buffers and bus fall times PCA9600 PCA9600 scl sx local master bus v ccm scl master i 2 c-bus cs slave bus capacitance cb buffered bus wiring capacitance cm master bus capacitance rm gnd (0 v) v ccb buffered expansion bus tx/rx tx/rx sx rb rs i 2 c-bus slave v ccs remote slave bus 002aac847 effective delay of scl at master: 115 + (rm cm) + (0.7 rb cb) (ns). c = f; r = w . fig 16. rising edge of scl at master is delayed (clock stretch) by buffer and bus rise times PCA9600 sx local master bus v ccm scl master i 2 c-bus cb buffered bus wiring capacitance cm master bus capacitance rm gnd (0 v) v ccb buffered expansion bus tx/rx tx/rx rb 002aac848
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 15 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer figure 15 , figure 16 , and figure 17 show the PCA9600 used to drive extended bus wiring with relatively large capacitances linking two i 2 c-bus nodes. it includes simpli?ed expressions for making the relevant timing calculations for 3.3 v or 5 v operation. because the buffers and the wiring introduce timing delays, it may be necessary to decrease the nominal scl frequency. in most cases the actual bus frequency will be lower than the nominal master timing due to bit-wise stretching of the clock periods. the delay factors involved in calculation of the allowed bus speed are: a the propagation delay of the master signal through the buffers and wiring to the slave. the important delay is that of the falling edge of scl because this edge requests the data or acknowledge from a slave. see figure 15 . b the effective stretching of the nominal low period of scl at the master caused by the buffer and bus rise times. see figure 16 . c the propagation delay of the slave's response signal through the buffers and wiring back to the master. the important delay is that of a rising edge in the sda signal. rising edges are always slower and are therefore delayed by a longer time than falling edges. (the rising edges are limited by the passive pull-up while falling edges are actively driven); see figure 17 . the timing requirement in any i 2 c-bus system is that a slave's data response (which is provided in response to a falling edge of scl) must be received at the master before the end of the corresponding low period of scl as appears on the bus wiring at the master. since all slaves will, as a minimum, satisfy the worst case timing requirements of their speed class (fast-mode, fm+, etc.), they must provide their response, allowing for the set-up time, within the minimum allowed clock low period, e.g., 450 ns (max.) for fm+ parts. in systems that introduce additional delays it may be necessary to extend the minimum clock low period to accommodate the effective delay of the slave's response. the effective delay of the slaves response equals the total delays in scl falling edge from effective delay of sda at master: 115 + 0.2(rs cs) + 0.7[(rb cb) + (rm cm)] (ns). c = f; r = w . fig 17. rising edge of sda at slave is delayed by the buffers and bus rise times PCA9600 PCA9600 sda sx local master bus v ccm sda master i 2 c-bus cs slave bus capacitance cb buffered bus wiring capacitance cm master bus capacitance rm gnd (0 v) v ccb buffered expansion bus tx/rx tx/rx sx rb rs i 2 c-bus slave v ccs remote slave bus 001aai158
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 16 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer the master reaching the slave ( figure 15 ) minus the effective delay (stretch) of the scl rising edge ( figure 16 ) plus total delays in the slave's response data, carried on sda, reaching the master ( figure 17 ). the master microcontroller should be programmed to produce a nominal scl low period as follows: (1) the actual low period will become (the programmed value + the stretching time b). when this actual low period is then less than the speci?ed minimum, the speci?ed minimum should be used. example 1: it is required to connect an fm+ slave, with rs cs product of 100 ns, to a 5 v fast-mode system also having 100 ns rm cm using two PCA9600s to buffer a 5 v bus with 4 nf loading and 160 w pull-up. calculate the allowed bus speed: delay a = 120 + 85 + (2.5 + [4 4]) 5 + 50 = 347.5 ns delay b = 115 + 100 + 70 = 285 ns delay c = 115 + 20 + 0.7(100 + 100) = 275 ns the maximum fm+ slave response delay must be < 450 ns so the programmed low period is calculated as: low 3 450 + 347.5 - 285 + 275 + 100 = 887.5 ns the actual low period will be 887.5 + 285 = 1173 ns, which is below the fast-mode minimum, so the programmed low period must be increased to (1300 - 285) = 1015 ns, so the actual low equals the 1300 ns requirement and this shows that this fast-mode system may be safely run to its limit of 400 khz. example 2: it is required to buffer a master with fm+ speed capability, but only 3 ma sink capability, to an fm+ bus. all the system operates at 3.3 v. the master rm cm product is 50 ns. only one PCA9600 is used. the fm+ bus becomes the buffered bus. the fm+ bus has 200 pf loading and 150 w pull-up, so its rb cb product is 30 ns. the fm+ slave has a speci?ed data valid time t vd;dat maximum of 300 ns. calculate the allowed maximum system bus speed. (note that the ?xed values in the delay equations represent the internal propagation delays of the PCA9600. only one PCA9600 is used here, so those ?xed values used below are taken from the characteristics.) the delays are: delay a = 40 + 56 + (2.5 + [4 0.2]) 3.3 = 107 ns delay b = 115 + 50 + 21 = 186 ns delay c = 70 + 0.7(50 + 30) = 126 ns the programmed low period is calculated as: scl low 3 300 + 117 - 186 + 126 + 50 = 407 ns scl low slave response delay to valid data on its sda a b c data set - up time ++ C + ( ) 3 ns
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 17 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer the actual low period will be 407 + 126 = 533 ns, which exceeds the minimum fm+ 500 ns requirement. this system requires the bus low period, and therefore cycle time, to be increased by 33 ns so the system must run slightly below the 1 mhz limit. the possible maximum speed has a cycle period of 1033 ns or 968 khz. there is an excel calculator which makes it easy to determine the maximum i 2 c-bus clock speed when using the PCA9600. the calculator and instructions can be found at www .nxp .com/cloc kspeedcalculator . fig 18. i 2 c-bus multipoint application PCA9600 sda rx scl tx ty ry 001aai065 12 v sx sy 12 v 12 v 3.3 v to 5 v 3.3 v to 5 v PCA9600 sx sy scl/sda PCA9600 sx sy scl/sda PCA9600 sx sy scl/sda PCA9600 sx scl sy sda no limit to the number of connected bus devices twisted-pair telephone wires, usb, or flat ribbon cables; up to 15 v logic levels, include v cc and gnd 3.3 v 3.3 v
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 18 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 10.2 negative undershoot below absolute minimum value the reason why the ic pin reverse voltage on pins tx and rx in t ab le 5 limiting v alues is speci?ed at such a low value, - 0.3 v, is not that applying larger voltages is likely to cause damage but that it is expected that, in normal applications, there is no reason why larger dc voltages will be applied. this absolute maximum speci?cation is intended to be a dc or continuous ratings and the nominal dc i 2 c-bus voltage low usually does not even reach 0 v. inside PCA9600 at every pin there is a large protective diode connected to the gnd pin and that diode will start to conduct when the pin voltage is more than about - 0.55 v with respect to gnd at 25 c ambient. figure 22 shows the measured characteristic for one of those diodes inside PCA9600. the plot was made using a curve tracer that applies 50 hz mains voltage via a series resistor, so the pulse durations are long duration (several milliseconds) and are reaching peaks of over 2 a when more than - 1.5 v is applied. the ic becomes very hot during this (1) tx output. (2) sx input. (1) tx/rx output. (2) sx input. fig 19. propagation sx to tx with v rx =v cc = 3.3 v (sx pull-up to 3.3 v; tx pull-up to 5.7 v) fig 20. propagation sx to tx with rx tied to tx; v cc = 3.3 v (sx pull-up to 3.3 v; tx pull-up to 5.7 v) (1) rx input. (2) sx output. fig 21. propagation rx to sx (sx pull-up to 3.3 v; v cc = 3.3 v; rx pull-up to 4.6 v) - 1 5 3 1 7 v cc (v) time (ns) 0 900 002aac932 200 100 300 400 500 600 700 800 0 2 4 6 (1) (2) (1) (2) - 1 5 3 1 7 v cc (v) time (ns) 0 900 002aac933 200 100 300 400 500 600 700 800 0 2 4 6 (1) (2) (1) (2) (2) - 1 5 3 1 7 v cc (v) time (ns) 0 900 002aac934 200 100 300 400 500 600 700 800 0 2 4 6 (1) (2) (1) (2)
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 19 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer testing but it was not damaged. whenever there is current ?owing in any of these diodes it is possible that there can be faulty operation of any ic. for that reason we put a speci?cation on the negative voltage that is allowed to be applied. it is selected so that, at the highest allowed junction temperature, there will be a big safety factor that guarantees the diode will not conduct and then we do not need to make any 100 % production tests to guarantee the published speci?cation. for the PCA9600, in speci?c applications, there will always be transient overshoot and ringing on the wiring that can cause these diodes to conduct. therefore we designed the ic to withstand those transients and as a part of the quali?cation procedure we made tests, using dc currents to more than twice the normal bus sink currents, to be sure that the ic was not affected by those currents. for example, the tx/ty and rx/ry pins were tested to at least - 80 ma which, from figure 22 , would be more than - 0.8 v. the correct functioning of the PCA9600 is not affected even by those large currents. the absolute maximum (dc) ratings are not intended to apply to transients but to steady state conditions. this explains why you will never see any problems in practice even if, during transients, more than - 0.3 v is applied to the bus interface pins of PCA9600. figure 22 diode char acter istic cur v e also explains how the general absolute maximum dc speci?cation was selected. the current at 25 c is near zero at - 0.55 v. the PCA9600 is allowed to operate with +125 c junction and that would cause this diode voltage to decrease by 100 2 mv = 200 mv. so for zero current we need to specify - 0.35 v and we publish - 0.3 v just to have some extra margin. remark: you should not be concerned about the transients generated on the wiring by a PCA9600 in normal applications and that is input to the tx/rx or ty/ry pins of another PCA9600. because not all ics that may be driven by PCA9600 are designed to tolerate negative transients, in section 10.2.1 example with questions and ans w ers we show they can be managed if required. fig 22. diode characteristic curve 002aaf063 voltage (v) - 2.0 0 - 0.5 - 1.5 - 1.0 - 10 - 10 3 - 10 2 - 10 - 1 - 1 0 - 10 4 diode current (ma)
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 20 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 10.2.1 example with questions and answers question: on a falling edge of tx we measure undershoot at - 800 mv at the linked tx, rx pins of the PCA9600 that is generating the low, but the PCA9600 data sheet speci?es minimum - 0.3 v. does this mean that we violate the data sheet absolute value? answer: for PCA9600 the - 0.3 v absolute maximum rating is not intended to apply to transients, it is a dc rating. as shown in figure 23 , there is no theoretical reason for any undershoot at the ic that is driving the bus low and no signi?cant undershoot should be observed when using reasonable care with the ground connection of the scope. it is more likely that undershoot observed at a driving PCA9600 is caused by local stray inductance and capacitance in the circuit and by the oscilloscope connections. as shown, undershoot will be generated by pcb traces, wiring, or cables driven by a PCA9600 because the allowed value of the i 2 c-bus pull-up resistor generally is larger than that required to correctly terminate the wiring. in this example, with no ic connected at the end of the wiring, the undershoot is about 2 v. fig 23. transients generated by the bus wiring 002aaf081 time (ns) 2 0 4 6 voltage (v) - 2 horizontal scale = 62.5 ns/div send receive 5 v rx tx sx PCA9600 send 300 w 5 v 2 meter cable 5 v 300 w gnd receive
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 21 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer question: we have 2 meters of cable in a bus that joins the tx/rx sides of two PCA9600 devices. when one tx drives low the other PCA9600 tx/rx is driven to - 0.8 v for over 50 ns. what is the expected value and the theoretically allowed value of undershoot? answer: because the cable joining the two PCA9600s is a transmission line that will have a characteristic impedance around 100 w and it will be terminated by pull-up resistors that are larger than that characteristic impedance there will always be negative undershoot generated. the duration of the undershoot is a function of the cable length and the input impedance of the connected ic. as shown in figure 24 , the transient undershoot will be limited, by the diodes inside PCA9600, to around - 0.8 v and that will not cause problems for PCA9600. those transients will not be passed inside the ic to the sx/sy side of the ic. question: if we input 800 mv undershoot at tx, rx pins, what kind of problem is expected? answer: when that undershoot is generated by another PCA9600 and is simply the result of the system wiring, then there will be no problems. question: will we have any functional problem or reliability problem? answer: no. fig 24. wiring transients limited by the diodes in PCA9600 002aaf082 time (ns) 2 0 4 6 voltage (v) - 2 horizontal scale = 62.5 ns/div send receive 5 v rx tx sx PCA9600 send 300 w 5 v 2 meter cable 5 v 300 w gnd receive sx rx tx 5 v
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 22 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer question: if we add 100 w to 200 w at signal line, the overshoot becomes slightly smaller. is this a good idea? answer: no, it is not necessary to add any resistance. when the logic signal generated by tx or ty of PCA9600 drives long traces or wiring with ics other than PCA9600 being driven, then adding a schottky diode (bat54a) as shown in figure 25 will clamp the wiring undershoot to a value that will not cause conduction of the ics internal diodes. fig 25. wiring transients limited by a schottky diode 002aaf083 time (ns) 2 0 4 6 voltage (v) - 2 horizontal scale = 62.5 ns/div receive 5 v rx tx sx PCA9600 send 300 w 5 v 2 meter cable 5 v 300 w gnd receive sx rx tx 5 v send 1 / 2 bat54a
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 23 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 11. package outline fig 26. package outline sot96-1 (so8) unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 99-12-27 03-02-18
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 24 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer fig 27. package outline sot505-1 (tssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.70 0.35 6 0 0.1 0.1 0.1 0.94 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.4 sot505-1 99-04-09 03-02-18 w m b p d z e 0.25 14 8 5 q a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 1.1 pin 1 index
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 25 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 12. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 12.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 12.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 12.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 26 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 12.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 28 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 8 and 9 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 28 . table 8. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 9. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 27 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 13. abbreviations msl: moisture sensitivity level fig 28. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 10. abbreviations acronym description cdm charged-device model esd electrostatic discharge hbm human body model i 2 c-bus inter-integrated circuit bus i/o input/output ic integrated circuit mm machine model pmbus power management bus smbus system management bus ttl transistor-transistor logic
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 28 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 14. revision history table 11. revision history document id release date data sheet status change notice supersedes PCA9600_4 20091111 product data sheet - PCA9600_3 modi?cations: ? t ab le 5 limiting v alues : added t ab le note [1] . ? added section 10.2 negativ e undershoot belo w absolute minim um v alue . PCA9600_3 20090903 product data sheet - PCA9600_2 PCA9600_2 20080813 product data sheet - PCA9600_1 PCA9600_1 20080602 product data sheet - -
PCA9600_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 11 november 2009 29 of 30 nxp semiconductors PCA9600 dual bidirectional bus buffer 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 15.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 15.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 16. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors PCA9600 dual bidirectional bus buffer ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 11 november 2009 document identifier: PCA9600_4 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 3 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 application information. . . . . . . . . . . . . . . . . . 12 10.1 calculating system delays and bus clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.2 negative undershoot below absolute minimum value . . . . . . . . . . . . . . . . . . . . . . . . 18 10.2.1 example with questions and answers. . . . . . . 20 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 12 soldering of smd packages . . . . . . . . . . . . . . 25 12.1 introduction to soldering . . . . . . . . . . . . . . . . . 25 12.2 wave and re?ow soldering . . . . . . . . . . . . . . . 25 12.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25 12.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 29 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 29 15.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 16 contact information. . . . . . . . . . . . . . . . . . . . . 29 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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